Takahashi Lab
home members research link


Gordon Moore's Law, as popularly defined as the number of transistors in one chip is doubled in 18 months, is becoming obsolete. Even though, the difficulties in design increase year by year since the progress in VLSI manufacturing technology still continues. The final performance of VLSI circuit is becoming strongly affected by physical design (layout) due to the smaller feature size. The optimization within the conventional clock synchronous circuit design methodology is saturated since the various costs due to the clock distribution increase. Therefore, design automation, especially high-quality design automation in physical design, is strongly requested recently. In our CAD group, the establishment of a new clock synchronous circuit design methodology, in which clock is distributed periodically but not necessarily to every clock element simultaneously, is pursued. Moreover, a new design methodology that combines design methodologies of synchronous circuit with clock and without clock is pursued. In our CAD group, we mainly focus on physical design problems such as clock, floorplan, placement, routing, and packaging in order to achieve the optimization of design targets such as area, speed, power consumption, and noise by the new design methodology which involves innovation of clock distribution. Moreover, we tackle higher level circuit synthesis in order to establish whole design methodology that takes physical design into account. Our final goal is the practical high-quality VLSI design system that contains low time complexity exact algorithms, heuristic algorithms, and stochastic algorithms.


Atsushi Takahashi
2-12-1-S3-58 Ookayama, Meguro-ku, Tokyo 152-8550, Japan
Department of Communications and Computer Engineering
Graduate School of Science and Engineering
Tokyo Institute of Technology

Phone: +81-3-5734-2665
FAX: +81-3-5734-2902


Ookayama Campus (Ookayama Area No.36. South Bldg. 3)

Last modified: April 17, 2019