Paper List 2024 (Atsushi Takahashi, Tokyo Tech)

Last modified: 11 April 2024

Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka.
Two-layer Bottleneck Channel Track Assignment for Analog VLSI.
IPSJ Trans. on System LSI Design Methodology, Vol.17, pp.xx-xx, June, 2024. (accepted)
Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi.
Accelerating extreme ultravolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula.
Journal of Micro/Nanopattern. Mater. Metrol (JM3). Vol.23, No.1, 014201, January 2, 2024.
( SPIE Digital Library )

Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi.
BCA Channel Routing to Minimize Wirelength for Generalized Channel Problem.
Proc. IEEE International Symposium on Circuits and Systems (ISCAS 2024), C2P-16, pp.??-??, Singapore, May 19-22, 2024. (poster) (accepted)
Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi.
Pre-training CNN for fast EUV lithography simulation including M3D effects.
Proc. SPIE 12954, DTCO and Computational Patterning III, 129540I, April 10, 2024.
(SPIE Digital Library)
Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka.
A Fast Three-layer Bottleneck Channel Track Assignment with Layout Constraints using ILP.
Proc. the 25th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI 2024), R1-10, pp.50-55, Taipei, Taiwan, March 11-12, 2024.

徐紫昂，田湯智，高橋篤司，モロンゴマチュー，南誠，西岡克也．
ダブルビア制約付きペア対称配線問題に対するSMTソルバを用いたテンプレート配線手法．
電子情報通信学会技術研究報告, vol.123, no.390, VLD2023-102, pp.18-23, 2024年2月28日.
谷口和弥，田湯智，高橋篤司，モロンゴマチュー，南誠，西岡克也．
端子上下配置3層ボトルネック配線に対するトラック割当て法の提案．
電子情報通信学会技術研究報告, vol.123, no.390, VLD2023-103, pp.24-29, 2024年2月28日.
Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi.
Single Trunk Routing Problem for Generalized Channel.
電子情報通信学会技術研究報告, vol.123, no.390, VLD2023-104, pp.37-42, 2024年2月28日.