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Paper List (Atsushi Takahashi)
Last modified: March 10, 2025
Routing Papers
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Zezhong Wang, Hiroto Nakayama, Masayuki Shimoda, Atsushi Takahashi, Kosuke Yanagidaira, Chikaaki Kodama.
UEO Channel Routing Algorithm to Alleviate Local Congestion for Generalized Channels.
IEICE Trans. Fundamentals, Vol.E108-A, No.9, pp.xx-xx, 2025. (accepted)
( IEICE Transactions Online )
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Zezhong Wang, Masayuki Shimoda, Atsushi Takahashi.
SDG Channel Routing to Minimize Wirelength for Generalized Channel.
IEICE Trans. Fundamentals, Vol.E108-A, No.3, pp.500-508, 2025.
( IEICE Transactions Online )
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Masayuki Shimoda, Atsushi Takahashi.
Gridless Gap Channel Routing with Variable-width Wires.
IEICE Trans. Fundamentals, Vol.E108-A, No.3, pp.517-524, 2025.
( IEICE Transactions Online )
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Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka.
A Fast Three-layer One-side Bottleneck Channel Routing with Layout Constraints using ILP.
IEICE Trans. Fundamentals, Vol.E108-A, No.3, pp.509-516, 2025.
( IEICE Transactions Online )
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Masayuki Shimoda, Atsushi Takahashi.
Gridless Gap Channel Routing to Minimize Wirelength.
IPSJ Trans. on System LSI Design Methodology, Vol.18, pp.2-9, February 2025.
(IPSJ TSLDM)
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Kazuya Taniguchi, Satoshi Tayu, Atsushi Takahashi, Mathieu Molongo, Makoto Minami, Katsuya Nishioka.
Two-layer Bottleneck Channel Track Assignment for Analog VLSI.
IPSJ Trans. on System LSI Design Methodology, Vol.17, pp.67-76, June 2024.
( IPSJ TSLDM )
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Shimpei Sato, Kano Akagi, Atsushi Takahashi.
A Fast Length Matching Routing Pattern Generation Method for Set-Pair Routing Problem Using Selective Pin-Pair Connections.
IEICE Trans. Fundamentals, Vol.E103-A, No.9, pp.1037-1044, 2020.
( IEICE Transactions Online )
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Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi, Chikaaki Kodama.
A Routing Method using Directed Grid-Graph for Self-Aligned Quadruple Patterning.
IEICE Trans. Fundamentals, Vol.E100-A, No.7, pp.1473-1480, 2017.
( IEICE Transactions Online )
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Yuta Nakatani, Atsushi Takahashi.
A Length Matching Routing Algorithm for Set-Pair Routing Problem.
IEICE Trans. Fundamentals, Vol.E98-A, No.12, pp.2565-2571, 2015.
( IEICE Transactions Online )
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Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi.
Single-Layer Trunk Routing Using Minimal 45-Degree Lines.
IEICE Trans. Fundamentals, Vol.E94-A, No.12, pp.2510-2518, 2011.
( IEICE Transactions Online )
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Yukihide Kohira, Atsushi Takahashi.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.
IEICE Trans. Fundamentals, Vol.E93-A, No.12, pp.2380-2388, 2010.
( IEICE Transactions Online )
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Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi.
A Fast Longer Path Algorithm for Routing Grid with Obstacles using Biconnectivity based Length Upper Bound.
IEICE Trans. Fundamentals, Vol.E92-A, No.12, pp.2971-2978, 2009.
( IEICE Transactions Online )
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A. Takahashi, H. Murata.
Three-Layer L-shaped Channel Routing Algorithm.
IPSJ Journal, Vol.40, No.4,
pp.1618-1625, Apr. 1999. (in Japanese)
( pdf 1045KB )
See also:
Proc. Karuizawa Workshop, pp.107-112, 1998. (in Japanese)
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Yasuhiro TAKASHIMA, Atsushi TAKAHASHI, and Yoji KAJITANI:
Assignment of Intervals to Parallel Tracks with Minimum Total Cross-Talk;
IEICE Trans. on Fundamentals,
E81-A [9] 1909-1915 (1998)
( IEICE Transactions Online )
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Yasuhiro TAKASHIMA, Atsushi TAKAHASHI, and Yoji KAJITANI:
Routability of FPGAs with Extremal Switch-Block Structures,
IEICE Trans. Fundamentals,
E81-A [5] 850-856 (1998)
( IEICE Transactions Online )
See also:
Proc. the European Design & Test Conference (ED&TC) 1996,
pp. 160-164, 1996.
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Hideki Mitsubayashi, Atsushi Takahashi, and Yoji Kajitani.
Cost-Radius Balanced Spanning/Steiner Trees.
IEICE Trans. Fundamentals,
Vol. E80-A, No. 4, pp. 689-694, 1997.
( IEICE Transactions Online )
See also:
Proc. IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) '96,
pp. 377-380, 1996.
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Takahashi, A., Yoji Kajitani
Peel-the-Box: A Concept of Switch-Box Routing and Tractable Problems.
INTEGRATION, the VLSI journal,
Vol. 14, No. 1, pp. 33-47, 1992.
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Atsushi Takahashi, Yoji Kajitani.
A Switch-Box Router 'BOX-PEELER' and Its Tractable Problems.
The Transactions of the IEICE,
Vol. E 72, No. 12, pp. 1367-1373, 1989.
( IEICE Transactions Online )
Lithography Papers
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Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi.
Weakly guiding approximation of three-dimensional waveguide model for extreme ultraviolet lithography simulation.
Journal of the Optical Society of America A, Vol.16, No.8, pp.1491-1499, 2024.
( OPTICA )
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Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi.
Accelerating extreme ultravolet lithography simulation with weakly guiding approximation and source position dependent transmission cross coefficient formula.
Journal of Micro/Nanopattern. Mater. Metrol (JM3). Vol.23, No.1, 014201, January 2, 2024.
( SPIE Digital Library )
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Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi.
Evaluation of convolutional neural network for fast extreme ultraviolet lithography simulation using imec 3nm node mask patterns.
Journal of Micro/Nanopattern. Mater. Metrol (JM3). Vol.22, No.2, 024201, June 15, 2023.
( SPIE Digital Library )
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Hiroyoshi Tanabe, Atsushi Takahashi.
Data augmentation in extreme ultraviolet lithography simulation using convolutional neural network.
Journal of Micro/Nanopattern. Mater. Metrol (JM3). Vol.21, No.4, 041602 October 14, 2022.
( SPIE Digital Library )
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Hiroyoshi Tanabe, Shimpei Sato, Atsushi Takahashi.
Fast EUV lithography simulation using convolutional neural network.
Journal of Micro/Nanopatterning, Materials and Metrology (JM3), Vol.20, No.4, 041202, September 24, 2021.
( SPIE Digital Library )
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Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama.
A Fast Process Variation Aware Mask Optimization Algorithm With a Novel Intensity Modeling.
IEEE Transactions on Very Large Scale Integration Systems (TVLSI),
Vol.25, No. 3, pp.998-1011, 2017.
(IEEE Xplore)
(IEEE Xplore)
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Ahmed Awad, Atsushi Takahashi, Satoshi Tanaka, Chikaaki Kodama.
Intensity Difference Map (IDM) Accuracy Analysis for OPC Efficiency Verification and Further Enhancement.
IPSJ Trans. on System LSI Design Methodology, Vol.10, pp.28-38, February 3, 2017.
( IPSJ TSLDM )
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Ahmed Awad, Atsushi Takahashi, Chikaaki Kodama.
A Fast Mask Manufacturability and Process Variation Aware OPC Algorithm with Exploiting a Novel Intensity Estimation Model.
IEICE Trans. Fundamentals, Vol.E99-A, No.12, pp.2363-2374, 2016.
( IEICE Transactions Online )
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Yukihide Kohira, Chikaaki Kodama, Tomomi Matsui, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka.
Yield-aware mask assignment by positive semidefinite relaxation in triple patterning using cut process.
Journal of Micro/Nanolithography, MEMS, and MOEMS (JM3), Vol.15, No.2, 021207, March 11, 2016.
( SPIE Digital Library )
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Chikaaki Kodama, Hirotaka Ichikawa, Koichi Nakayama, Fumiharu Nakajima,
Shigeki Nojima, Toshiya Kotani, Takeshi Ihara and Atsushi Takahashi.
Self-Aligned Double and Quadruple Patterning Aware Grid Routing Method.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),
Vol.34, No. 5, pp.753-765, May 2015.
(IEEE Xplore)
(IEEE Xplore)
Synchronous Circuits Papers
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Yuta Ukon, Shimpei Sato, Atsushi Takahashi.
Design Method of Variable-Latency Circuit with Tunable Approximate Completion-Detection Mechanism.
IEICE Trans. Electronics, Vol.E104-C, No.7, pp.309-318, 2021.
( IEICE Transactions Online )
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Shimpei Sato, Eijiro Sassa, Yuta Ukon, Atsushi Takahashi.
A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution.
IEICE Trans. Fundamentals, Vol.E102-A, No.12, pp.1760-1769, 2019.
( IEICE Transactions Online )
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Yukihide Kohira, Atsushi Takahashi.
2-SAT based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.
IEICE Trans. Fundamentals, Vol.E97-A, No.12, pp.2459-2466, 2014.
( IEICE Transactions Online )
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Yukihide Kohira, Shuhei Tani, Atsushi Takahashi.
Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.
IEICE Trans. Fundamentals, Vol.E92-A, No.4, pp.1106-1114, 2009.
( IEICE Transactions Online )
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Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi.
A Fast Clock Scheduling for Peak Power Reduction in LSI.
IEICE Trans. Fundamentals, Vol.E91-A, No.12, pp.3803-3811, 2008.
( IEICE Transactions Online )
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Yukihide Kohira, Atsushi Takahashi.
A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.
IEICE Trans. Fundamentals, Vol.E91-A, No.10, pp.3030-3037, 2008.
( IEICE Transactions Online )
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Bakhtiar Affendi Rosdi, Atsushi Takahashi.
Low Area Pipelined Circuits by the Replacement of Registers with Delay Elements.
IEICE Trans. Fundamentals, Vol.E90-A, No.12, pp.2736-2742, 2007.
( IEICE Transactions Online )
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Yukihide Kohira, Atsushi Takahashi.
Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.
IEICE Trans. Fundamentals, Vol.E90-A, No.4, pp.800-807, 2007.
( IEICE Transactions Online )
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Bakhtiar Affendi Rosdi, Atsushi Takahashi.
Multi-clock Cycle Paths and Clock Scheduling for
Reducing the Area of Pipelined Circuits.
IEICE Trans. Fundamentals, Vol.E89-A, No.12, pp.3435-3442, 2006.
( IEICE Transactions Online )
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Atsushi Takahashi.
Practical Fast Clock-Schedule Design Algorithms.
IEICE Trans. Fundamentals, Vol.E89-A, No.4, pp.1005-1011, 2006.
( IEICE Transactions Online )
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Y. Kohira, A. Takahashi.
Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion.
IEICE Trans. Fundamentals, Vol.E88-A, No.4, pp.892-898, 2005.
( IEICE Transactions Online )
See also:
In Proc. the 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS 2004), pp.533-536, December 6-9, 2004.
( IEEE Xplore )
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H. Matsumura and A. Takahashi.
Delay Variation Tolerant Clock Scheduling for Semi-synchronous Circuits.
In Proc. Asia-Pacific Conference on Circuits and Systems (APCCAS) '02.
Vol.1, pp.165-170, 2002.
( IEEE Xplore )
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M. Saitoh, M. Azuma, and A. Takahashi.
A Clustering Based Fast Clock Schedule Algorithm for Light Clock-Trees
IEICE Trans. Fundamentals, Vol.E85-A, No.12, pp.2756-2763, 2002.
( IEICE Transactions Online )
See also:
In Proc. Design Automation and Test in Europe Conference and Exhibition (DATE),
pp. 240-244, 2001.
( pdf 141KB )
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K. Kurokawa, T. Yasui, Y. Matsumura, M. Toyonaga, and A. Takahashi.
A High-Speed and Low-Power Clock Tree Synthesis by Dynamic Clock Scheduling
IEICE Trans. Fundamentals, Vol.E85-A, No.12, pp.2746-2755, 2002.
( IEICE Transactions Online )
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S. Ishijima, T. Utsumi, T. Oto, and A. Takahashi.
A Semi-Synchronous Circuit Design Method by Clock Tree Modification
IEICE Trans. Fundamentals, Vol.E85-A, No.12, pp.2596-2602, 2002.
( IEICE Transactions Online )
( pdf 100KB )
See also:
In Proc. the Workshop on Synthesis and System Integration of
Mixed Technologies (SASIMI),
pp.382-386, 2001.
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K. Kurokawa, T. Yasui, M. Toyonaga, and A. Takahashi.
A Practical Clock Tree Synthesis for Semi-Synchronous Circuits.
IEICE Transactions on Fund., Vol.E84-A, No.11, pp.2705-2713, 2001.
( IEICE Transactions Online )
See also: Proc. ACM International Symposium on Physical Design (ISPD),
pp.159-164, 2000.
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T. Yoda and A. Takahashi.
Clock Schedule Design for Minimum Realization Cost.
IEICE Transactions on Fundamentals, Vol.E83-A, No.12, pp.2552-2557, 2000.
( IEICE Transactions Online )
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K. Inoue, W. Takahashi, A. Takahashi, Y. Kajitani.
Schedule-Clock-Tree Routing for Semi-Synchronous Circuits.
IEICE Transactions on Fundamentals, Vol.E82-A, No.11,
pp.2431-2439, Nov. 1999
( IEICE Transactions Online )
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T. Yoda, and A. Takahashi.
Clock Period Minimization of Semi-Synchronous Circuits
by Gate-Level Delay Insertion.
IEICE Transactions on Fundamentals, Vol.E82-A, No.11,
pp.2383-2389, Nov. 1999.
( IEICE Transactions Online )
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Atsushi Takahashi, Wataru Takahashi, and Yoji Kajitani.
Clock-Routing Driven Layout Methodology for Semi-Synchronous Circuit Design.
Proc. 1997 IEEE/ACM International Workshop on Timing Issues
in the Specification and Synthesis of Digital Systems (TAU),
pp. 63-66, 1997.
( pdf 109KB )
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Atsushi Takahashi, Kazunori Inoue, and Yoji Kajitani.
Clock-Tree Routing Realizing a Clock-Schedule for Semi-Synchronous Circuits.
Proc. IEEE/ACM International Conference on Computer Aided Design (ICCAD) '97,
pp. 260-265, 1997.
( pdf 171KB )
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Atsushi Takahashi and Yoji Kajitani.
Performance and Reliability Driven
Clock Scheduling of Sequential Logic Circuits.
Proc. Asia and South Pacific Design Automation Conference (ASPDAC) '97,
pp. 37-42, 1997.
( IEEE Xplore )
( pdf 158KB )
Package Routing Papers
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Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi.
MILP-based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundamentals, Vol.E92-A, No.12, pp.2998-3006, 2009.
( IEICE Transactions Online )
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Yoichi Tomioka, Atsushi Takahashi.
Routability Driven Via Assignment Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundamentals, Vol.E92-A, No.6, pp.1433-1441, 2009.
( IEICE Transactions Online )
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Yoichi Tomioka, Atsushi Takahashi.
Routing of Monotonic Parallel and Orthogonal Netlists
for Single-Layer Ball Grid Array Packages.
IEICE Trans. Fundamentals, Vol.E89-A, No.12, pp.3551-3559, 2006.
( IEICE Transactions Online )
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Yukiko Kubo, Atsushi Takahashi.
Global Routing by Iterative Improvements for 2-Layer Ball Grid Array Packages.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
(TCAD), Vol.25, No.4, pp.725-733, April 2006.
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Y. Kubo, A. Takahashi.
A Via Assignment and Global Routing Method for 2-Layer Ball Grid Array Packages.
IEICE Trans. Fundamentals, Vol.E88-A, No.5, pp.1283-1289, 2005.
( IEICE Transactions Online )
Placement and Floorplan Papers
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Yiqiang Sheng, Atsushi Takahashi.
A Novel High-Performance Heuristic Algorithm with Application to Physical Design Optimization.
IEICE Trans. Fundamentals, Vol.E97-A, No.12, pp.2418-2426, 2014.
( IEICE Transactions Online )
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Yiqiang Sheng, Atsushi Takahashi.
A New Variation of Adaptive Simulated Annealing for 2D/3D Packing Optimization.
IPSJ Trans. on System LSI Design Methodology, Vol.6, pp.94-100, August 5, 2013.
(
IPSJ TSLDM ,
T2R2
)
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H. Yamazaki, N. Mikami, and A. Takahashi.
A Module Placement Algorithm by Force-directed Method without Overlapping.
IPSJ Journal, Vol.43, No.5, pp.1304-1314, 2002. (in Japanese)
( pdf 457KB )
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M. Tsuboi, C. Kodama, K. Sakanushi, K. Fujiyoshi, and A. Takahashi.
Linear Time Decodable Rectangular Dissection to Represent Arbitrary Packing
Using Q-Sequence.
In Proc. the Workshop on Synthesis and System Integration of
Mixed Technologies (SASIMI),
pp.272-278, 2001.
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Z.L. Wu, S. Nakatake, A. Takahashi, and Y. Kajitani.
Hierarchical BSG Floorplan for Hierarchical VLSI Circuit Design.
IEICE Transactions, Vol.J83-A, No.10, pp.1161-1168, 2000. (in Japanese)
( IEICE Transactions Online (in Japanese) )
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Tomonori IZUMI, Atsushi TAKAHASHI, and Yoji KAJITANI:
Air-pressure model and fast algorithms for zero-wasted-area layout of general floorplan;
IEICE Trans. Fundamentals,
E81-A [5] 857-865 (1998)
( IEICE Transactions Online )
See also:
Proc. Asia and South Pacific Design Automation Conference (ASPDAC) '98,
563-570 (1998)
Partitioning Papers
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Masato Inagi, Yasuhiro Takashima, Yuichi Nakamura, Atsushi Takahashi.
Optimal Time-Multiplexing in Inter-FPGA Connections for Accelerating Multi-FPGA Prototyping Systems.
IEICE Trans. Fundamentals, Vol.E91-A, No.12, pp.3539-3547, 2008.
( IEICE Transactions Online )
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Kengo R. AZEGAMI, Masato INAGI, Atsushi TAKAHASHI, and Yoji KAJITANI.
An Improvement of Network-Flow Based Multi-Way Circuit Partitioning Algorithm.
IEICE Trans. Fundamentals, Vol.E85-A, No.3, pp.655-663, 2002.
( IEICE Transactions Online )
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Kengo R. AZEGAMI, Atsushi TAKAHASHI, Yoji KAJITANI.
An Efficient Algorithm to Extract an Optimal Sub-Circuit by
the Minimum Cut.
IEICE Trans. Fundamentals, Vol.E84-A, No.5, pp.1301-1308, 2001.
( IEICE Transactions Online )
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K. R. Azegami, A. Takahashi, and Y. Kajitani.
Enumerating the min-cut edges with applications to graph partition under
size constraints.
Proc. IEEE International Symposium on Circuits and Systems (ISCAS), Vol.~VI,
pp.174-177, Jun. 1999.
Synthesis Papers
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E. Bozorgzadeh, S. Ghiasi, A. Takahashi, and M. Sarrafzadeh.
Optimal Integer Delay-Budget Assignment on Directed Acyclic Graphs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,
Vol.23, No. 8, pp.1184-1199, 2004.
( IEEE Xplore )
See also:
In Proc. 40th Design Automation Conference, pp.920-925, 2003.
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Tomonori IZUMI, Toshihiko YOKOMARU, Atsushi TAKAHASHI, and Yoji KAJITANI:
Computational Complexity Analysis of Set-Bin-Packing Problem;
IEICE Trans. on Fundamentals,
E81-A [5] 842-849 (1998)
( IEICE Transactions Online )
See also:
In Proc. International Symposium on Circuits And Systems (ISCAS),
WAA11-2 (1998)
Pathwidth Papers
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Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani.
Minimal Forbidden Minors for the Family of Graphs
with Proper-Path-Width at Most Two.
IEICE Trans. Fundamentals,
Vol. E 78-A, No. 12, pp. 1828-1839, 1995.
( IEICE Transactions Online )
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Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani.
Universal Graphs for Graphs with Bounded Path-Width.
IEICE Trans. Fundamentals,
Vol. E 78-A, No. 4, pp. 458-462, 1995.
( IEICE Transactions Online )
See also:
Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS) '92,
pp. 419-423, 1992.
-
Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani.
On the Proper-Path-Decomposition of Trees.
IEICE Trans. Fundamentals,
Vol. E 78-A, No. 1, pp. 131-136, 1995.
( IEICE Transactions Online )
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Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani.
Mixed-Searching and Proper-Path-Width.
Theoretical Computer Science,
Vol. 137, No. 2, pp. 253-268, 1995.
( ScienceDirect )
See also: Proc. Second Annual International Symposium on Algorithms,
Lecture Notes in Computer Science,
Vol. 557, pp. 61-71, 1991.
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Atsushi Takahashi, Shuichi Ueno, Yoji Kajitani.
Minimal Acyclic Forbidden Minors for the Family of Graphs
with Bounded Path-Width.
Discrete Mathematics, Vol. 127, pp. 293-304, 1994.
( ScienceDirect )
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